FIG. 1 provides a block diagram for outputting data from a general integrated circuit capable of storing data.
In the integrated circuit for outputting data, there are included a command translating unit 110 for translating a command that is received from external to provide a read command internal signal to a data storing unit 130, an address input unit 120 for receiving and buffering an address to output it, the data storing unit 130 for storing data to read, an output control signal generating unit 140 for receiving the read command internal signal and counting an internal clock to output an control signal, and an output unit 150 for outputting the data that is inputted from the data storing unit 130 at a desired clock timing under control of the control signal that is outputted from the output control signal generating unit 140.
FIG. 2 is a detailed block diagram of an output control signal generating unit 140 shown in FIG. 1.
The output control signal generating unit 140 includes a clock count unit 210 for receiving the read command internal signal to count the internal clock, and a control signal generating unit 220 for receiving a count signal that is outputted from the clock count unit 210 to output the control signal for controlling an outputting unit 150 in synchronous with the internal clock.
FIG. 3 describes a block diagram of an output control signal generating unit 140 in prior art, when CL [CAS(Column Address Strobe) Latency] is 5, where CL is an interval between a command clock and a first rising edge of a data strobe signal and the data strobe signal is a signal that is enabled for capturing data.
A first level detecting unit 301 counts the internal clock from the moment of inputting of the read command internal signal to output a count-1 signal Count1. A second level detecting unit 302 counts the inverted internal clock from the moment of receiving of the first count signal Count1 to output a count 1.5 signal Count1.5. In this way, a third to an eighth level detecting units 303-308 output a count 2 signal to a count 4.5 signal, respectively. A ninth level detecting unit 309 and a tenth level detecting unit 310 of the control signal generating unit 220 output an output control signal 5 and an output control signal 5.5 by using the output (count 4.5) of the eighth level detecting unit 308 and the output of the ninth level detecting unit 310 based on the internal clock and the inverted internal clock, respectively.
FIG. 4 shows a timing diagram when the output control signal generating unit in FIG. 3 operates at a low frequency.
When the read command is inputted at an external clock 0 and the desired data is outputted at an external clock 5, the output control signal 5 is generated in synchronous with the internal clock corresponding to the external clock 5. At that time, because a delay between the internal clock and the external clock, i.e., the time that is required to generate the read command internal signal from the read command is not longer than one cycle of the clock at a low frequency, after activation of the read command internal signal, the internal clock can be counted from the internal clock corresponding to the external clock 1, and the output control signal 5 is generated in synchronous with the internal clock corresponding to the external clock timing 5.
However, because the delay between the internal clock and the external clock, i.e., the time that is required to generated the read command internal signal from the read command is longer than one cycle of the clock at a high frequency, the internal clock timing that is initially counted could not be the external clock timing 1 after the read command internal signal is activated.
FIG. 5 shows a timing diagram when the output control signal generating unit in FIG. 3 operates at a high frequency. For example, the internal clock that is initially counted corresponds to the external clock 3 after the read command internal signal is activated.
Because the output control signal 5 is generated in synchronous with the internal clock corresponding to the external clock 7, desired data is not to be outputted at the desired external clock 5. That is, within a higher frequency region where the sum of the delay between the internal clock and the external clock and the time required to generate the read command internal signal from the read command is longer than one cycle of the clock, the conventional clock count unit happened to have a problem in counting the clock to output data with the CL.